A fast SOP minimizer for logic funcions described by many product terms

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 757-764

  Fišer, Petr ^a   Toman, David ^a  

^a CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

Author keywords

Espresso; Logic functions; SOP; Ternary tree; Two level minimization

Indexed keywords

BENCHMARK CIRCUIT; BOOLEAN OPERATIONS; FUNCTION REPRESENTATIONS; INCOMPLETELY SPECIFIED FUNCTIONS; LOGIC FUNCTIONS; MINIMIZATION ALGORITHMS; MINIMIZATION METHODS; PRE-PROCESSING; PRODUCT TERM; RUNTIMES; TERNARY TREE;

ALGORITHMS; IMAGE RETRIEVAL;

OPTIMIZATION;

EID: 74549215147     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.157     Document Type: Conference Paper

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