메뉴 건너뛰기




Volumn , Issue , 2008, Pages 122-127

Fast Boolean minimizer for completely specified functions

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS; MEMORY CONSUMPTION; MINIMIZATION ALGORITHMS;

EID: 50649111212     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2008.4538768     Document Type: Conference Paper
Times cited : (6)

References (20)
  • 2
    • 50649093414 scopus 로고    scopus 로고
    • Agarwal, Kime, Saluja: A tutorial on BIST, part 1: Principles. IEEE Design & Test of Computers, 10, No.1 March 1993, pp.73-83, part 2: Applications, No.2 June 1993, pp.69-77
    • Agarwal, Kime, Saluja: "A tutorial on BIST, part 1: Principles". IEEE Design & Test of Computers, vol. 10, No.1 March 1993, pp.73-83, part 2: Applications, No.2 June 1993, pp.69-77
  • 3
    • 33845331515 scopus 로고
    • Minimization of Boolean functions
    • Nov
    • E.J. McCluskey, "Minimization of Boolean functions", The Bell System Technical Journal, 35, No. 5, Nov. 1956, pp. 1417-1444
    • (1956) The Bell System Technical Journal , vol.35 , Issue.5 , pp. 1417-1444
    • McCluskey, E.J.1
  • 4
    • 0016102508 scopus 로고
    • MINI: A heuristic approach for logic minimization
    • IBM Journal of Res. & Dev, Sept
    • S.J. Hong, R.G. Cain and D.L. Ostapko, "MINI: A heuristic approach for logic minimization", IBM Journal of Res. & Dev., Sept. 1974, pp.443-458
    • (1974) , pp. 443-458
    • Hong, S.J.1    Cain, R.G.2    Ostapko, D.L.3
  • 6
    • 84939338348 scopus 로고
    • Multiple-valued minimization for PLA optimization
    • Sept
    • R.L. Rudell and A.L. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization", IEEE Trans. on CAD, 6(5): 725-750, Sept.1987
    • (1987) IEEE Trans. on CAD , vol.6 , Issue.5 , pp. 725-750
    • Rudell, R.L.1    Sangiovanni-Vincentelli, A.L.2
  • 7
    • 0027277648 scopus 로고    scopus 로고
    • ESPRESSO-SIGNATURE: A new exact minimizer for logic functions
    • P. McGeer et al., "ESPRESSO-SIGNATURE: A new exact minimizer for logic functions", Proc. DAC'93
    • Proc. DAC'93
    • McGeer, P.1
  • 8
    • 0035209084 scopus 로고    scopus 로고
    • J. Hlavička, P. Fišer, BOOM - a Heuristic Boolean Minimizer, Proc. ICCAD 2001, San Jose, Cal. (USA), 4.-8.11.2001, 439-442
    • J. Hlavička, P. Fišer, "BOOM - a Heuristic Boolean Minimizer", Proc. ICCAD 2001, San Jose, Cal. (USA), 4.-8.11.2001, 439-442
  • 9
    • 0347596514 scopus 로고    scopus 로고
    • BOOM - A Heuristic Boolean Minimizer
    • P. Fišer, J. Hlavička, "BOOM - A Heuristic Boolean Minimizer", Computers and Informatics, Vol. 22, 2003, No. 1, pp. 19-51
    • (2003) Computers and Informatics , vol.22 , Issue.1 , pp. 19-51
    • Fišer, P.1    Hlavička, J.2
  • 11
    • 50649120721 scopus 로고    scopus 로고
    • P. Fišer, H. Kubátová, Two-Level Boolean Minimizer BOOM-II, Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany, 23.-24.9.2004, pp. 221-228
    • P. Fišer, H. Kubátová, "Two-Level Boolean Minimizer BOOM-II", Proc. 6th Int. Workshop on Boolean Problems (IWSBP'04), Freiberg, Germany, 23.-24.9.2004, pp. 221-228
  • 12
    • 34547978295 scopus 로고    scopus 로고
    • P. Fišer, H. Kubátová, Flexible Two-Level Boolean Minimizer BOOM II and Its Applications, Proc. 9th Euromicro Conference on Digital Systems Design (DSD'06), Cavtat, (Croatia), 30.8. - 1.9.2006, pp. 369-376
    • P. Fišer, H. Kubátová, "Flexible Two-Level Boolean Minimizer BOOM II and Its Applications", Proc. 9th Euromicro Conference on Digital Systems Design (DSD'06), Cavtat, (Croatia), 30.8. - 1.9.2006, pp. 369-376
  • 13
    • 50649123638 scopus 로고    scopus 로고
    • P. Fišer, J. Hlavička, Implicant Expansion Method used in the BOOM Minimizer. Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'01), Gyor (Hungary), 18.-20.4.2001, pp. 291-298
    • P. Fišer, J. Hlavička, "Implicant Expansion Method used in the BOOM Minimizer". Proc. IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS'01), Gyor (Hungary), 18.-20.4.2001, pp. 291-298
  • 14
    • 0002609165 scopus 로고
    • A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan
    • F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan", Proc. of ISCAS 1985, pp. 663-698
    • (1985) Proc. of ISCAS , pp. 663-698
    • Brglez, F.1    Fujiwara, H.2
  • 15
    • 0024913805 scopus 로고
    • Combinational Profiles of Sequential Benchmark Circuits
    • F. Brglez, D. Bryan and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", Proc. of ISCAS, pp. 1929-1934, 1989
    • (1989) Proc. of ISCAS , pp. 1929-1934
    • Brglez, F.1    Bryan, D.2    Kozminski, K.3
  • 17
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • June
    • S. B. Akers, "Binary decision diagrams", IEEE Trans.on Computers, Vol. C-27. No. 6, June 1978, pp. 509-516.
    • (1978) IEEE Trans.on Computers , vol.C-27 , Issue.6 , pp. 509-516
    • Akers, S.B.1
  • 19
    • 50649098743 scopus 로고
    • A Study of the Aplication of Binary Decision Diagrams to Multi-level Logic Synthesis
    • Universitá Catholique de Louvain, Bélgica
    • R. P. Jacobi, "A Study of the Aplication of Binary Decision Diagrams to Multi-level Logic Synthesis". Nivel de doutorado, Universitá Catholique de Louvain, Bélgica, 1993.
    • (1993) Nivel de doutorado
    • Jacobi, R.P.1
  • 20
    • 0036311458 scopus 로고    scopus 로고
    • Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits
    • 1 January
    • L. Jozwiak, A. Slusarczyk and M. Perkowski,."Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits" ,VLSI Design, Volume 14, Number 1, 1 January 2002, pp. 107-122
    • (2002) VLSI Design , vol.14 , Issue.1 , pp. 107-122
    • Jozwiak, L.1    Slusarczyk, A.2    Perkowski, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.