An efficient multiple-parity generator design for on-line testing on FPGA

Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

Volumn , Issue , 2008, Pages 96-99

  Fišer, Petr ^a   Kubalík, Pavel ^a   Kubátová, Hana ^a  

^a CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

DUPLEX SYSTEMS; GENERATOR DESIGNS; LINE TESTING; ON-LINE DIAGNOSTICS; PARITY BITS;

DESIGN; NETWORKS (CIRCUITS); SYSTEMS ANALYSIS;

ARCHITECTURAL DESIGN;

EID: 57649229761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2008.46     Document Type: Conference Paper

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