Term trees in application to an effective and efficient ATPG for AND-EXOR and AND-OR circuits

VLSI Design

Volumn 14, Issue 1, 2002, Pages 107-122

  Józwiak, Lech ^a   Ślusarczyk, Aleksander ^a   Perkowski, Marek ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b Portland State University   (United States)

Author keywords

Automatic test pattern generation; Circuit structure representation; Decision diagrams; Structural fault model; Term trees

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; DATA COMPRESSION; DECISION THEORY; LOGIC CIRCUITS; TREES (MATHEMATICS);

TERM TREES;

DIGITAL CIRCUITS;

EID: 0036311458     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1080/10655140290009837     Document Type: Article

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