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Volumn , Issue , 2009, Pages 27-31

Energy and bandwidth aware mapping of IPs onto regular NoC architectures using multi-objective genetic algorithms

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH-AWARE; C-BASED DESIGN; COMMUNICATION SYNTHESIS; LINK BANDWIDTH; MINIMIZING ENERGY; MULTI-MEDIA; MULTI-OBJECTIVE GENETIC ALGORITHM; NETWORK-ON-CHIP ARCHITECTURES; NOC ARCHITECTURES; ONE-ONE MAPPING; OPTIMAL SOLUTIONS; PARETO OPTIMAL SOLUTIONS; PERFORMANCE EVALUATION; REAL-LIFE APPLICATIONS; TOPOLOGICAL MAPPING;

EID: 74549160413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2009.5335684     Document Type: Conference Paper
Times cited : (26)

References (9)
  • 1
    • 3042565282 scopus 로고    scopus 로고
    • N. Banerjee, P. Vellanki, and K. Chatha. A power and performance model for network-on-chip architectures. Proc. Design, Automation and Test in Europe, pages 1250-1255, 2004.
    • N. Banerjee, P. Vellanki, and K. Chatha. A power and performance model for network-on-chip architectures. Proc. Design, Automation and Test in Europe, pages 1250-1255, 2004.
  • 4
    • 84954421164 scopus 로고    scopus 로고
    • Energy-aware mapping for tile-based noc architectures under performance constraints
    • September 1-6
    • J. Hu and R. Marculescu. Energy-aware mapping for tile-based noc architectures under performance constraints. Asia & South Pacific Design Automation Conference, pages 53-57, September 1-6, 2003.
    • (2003) Asia & South Pacific Design Automation Conference , pp. 53-57
    • Hu, J.1    Marculescu, R.2
  • 5
    • 84893760422 scopus 로고    scopus 로고
    • Exploiting the routing flexibility for energy/performance aware mapping for regular noc architectures
    • September 1-6
    • J. Hu and R. Marculescu. Exploiting the routing flexibility for energy/performance aware mapping for regular noc architectures. Proceedings Design, Automation and Test in Europe, pages 688-693, September 1-6, 2003.
    • (2003) Proceedings Design, Automation and Test in Europe , pp. 688-693
    • Hu, J.1    Marculescu, R.2
  • 6
    • 84944322013 scopus 로고    scopus 로고
    • A two-step genetic algorithm for mapping task graphs to a network-on-chip architecture
    • September 1-6
    • T. Lei and S. Kumar. A two-step genetic algorithm for mapping task graphs to a network-on-chip architecture. Euro Micro Symposium on Digital Systems Design, pages 53-57, September 1-6, 2003.
    • (2003) Euro Micro Symposium on Digital Systems Design , pp. 53-57
    • Lei, T.1    Kumar, S.2
  • 8
    • 27944442417 scopus 로고    scopus 로고
    • Isis: A genetic algorithm based technique for custom on-chip interconnection network synthesis
    • K. Srinivasan and K. Chatha. Isis: A genetic algorithm based technique for custom on-chip interconnection network synthesis. Proc. of the 18th Int'l Conf. on VLSI Design, 2005.
    • (2005) Proc. of the 18th Int'l Conf. on VLSI Design
    • Srinivasan, K.1    Chatha, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.