An on chip network inside a FPGA for run-time reconfigurable low latency grid communication

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 539-546

  Strunk, Jochen ^a   Volkmer, Toni ^a   Rehm, Wolfgang ^a   Schick, Heiko ^b  

^a CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNEL; COMMUNICATION TASK; CONFIGURABLE NETWORKS; LOW LATENCY; LOW-LATENCY COMMUNICATION; MULTIPLE USER; MUTUAL INTERFERENCE; NEW APPLICATIONS; ON-CHIP COMMUNICATION NETWORKS; ON-CHIP NETWORKS; ON-DEMAND; PARALLEL COMMUNICATION; PROOF OF CONCEPT; RE-CONFIGURABLE; RUN-TIME RECONFIGURABLE; RUNTIME ENVIRONMENTS; SILICON NETWORKS;

COMMUNICATION; ELECTRIC NETWORK TOPOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; REAL TIME SYSTEMS;

EMBEDDED SYSTEMS;

EID: 74549117156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.133     Document Type: Conference Paper

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