Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Strunk, Jochen ^a   Volkmer, Toni ^a   Stephan, Klaus ^a   Rehm, Wolfgang ^a   Schickz, Heiko ^b  

^a CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAM; CLOCK SPEED; CREATION PROCESS; DESIGN CONSIDERATIONS; ON-DEMAND; RE-CONFIGURABLE; RECONFIGURABILITY; RECONFIGURABLE MODULE; RUN TIME RECONFIGURATION; RUN-TIME RECONFIGURABLE; RUNTIMES; STATE OF THE ART;

DISTRIBUTED PARAMETER NETWORKS; RESEARCH;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449970106     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161221     Document Type: Conference Paper

References (10)

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