An efficient run-time router for connecting modules in FPGAs

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 125-130

  Suris, Jorge ^a   Patterson, Cameron ^a   Athanas, Peter ^a  

^a State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAD SOFTWARES; CHANNEL ROUTING ALGORITHMS; COMPACT ROUTING; DETERMINISTIC EXECUTIONS; EFFICIENT; EXECUTION TIMES; FPGA DESIGNS; MEMORY USAGES; ORDERS OF MAGNITUDES; ROUTING RESOURCES;

COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; ROUTING ALGORITHMS;

COMPUTER NETWORKS;

EID: 54949139674     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629919     Document Type: Conference Paper

References (8)

1. Xilinx Inc., XAPP290: Two flows for partial reconfiguration: Module based or difference based, September 2004.
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3. L. McMurchie and C. Ebeling, "PathFinder: a negotiation-based performance-driven router for FPGAs," in FPGA '95: Proc. of the 1995 ACM Third Int. Symp. on Field Programmable Gate Arrays, 1995, pp. 111-117.
4. S. A. Guccione and D. Levi, "XBI: A lava-based interface to FPGA hardware." in Configurable Computing: Technology and Applications, Proc. SPIE 3526.
5. N. Steiner and P. Athanas, "An alternate wire database for Xilinx FPGAs." in FCCM '04: Proc. of the 12th Annual IEEE Symp. on Field-Programmable Custom Computing Machines. IEEE Computer Society, 2004, pp. 336-337.
6. M. Hiibner, C. Schuck, and J. Becker, "Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs." in IPDPS. IEEE, 2006.
7. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Field-Programmable Logic and Applications, W. Luk, P. Y. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, 1997, pp. 213-222.
8. C. Mulpuri and S. Hauck, "Runtime and quality tradeoffs in FPGA placement and routing," in FPGA '01: Proc. of the 2001 ACM/SIGDA Ninth Int. Symp. on Field Programmable Gate Arrays. New York, NY USA: ACM Press, 2001, pp. 29-36.