The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 427-430

  Chen, Ping ^a   Ye, Andy ^a  

^a RYERSON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STRUCTURES; DIGITAL SIGNAL PROCESSORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUCTION MOTORS; LOGIC GATES; SIGNAL PROCESSING;

AREA EFFICIENCIES; AREA REDUCTIONS; AREA SAVINGS; CONFIGURATION MEMORIES; CONNECTION BLOCKS; CPU CORES; DIGITAL SIGNALS; EFFICIENT; FIELD-PROGRAMMABLE GATE ARRAYS; IN FIELDS; MEMORY CELLS; NEW OPPORTUNITIES; PATTERN DESIGNS; PROCESSING ELEMENTS; ROUTING; ROUTING RESOURCES; SPARSE SWITCHES;

DATA STORAGE EQUIPMENT;

EID: 54949087925     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629975     Document Type: Conference Paper

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