The impact of back-side Cu contamination on 3D stacking architecture

Electrochemical and Solid-State Letters

Volumn 13, Issue 2, 2010, Pages

  Yang, Yu ^a,b   Labie, Riet ^a   Richard, Olivier ^a   Bender, Hugo ^a   Zhao, Chao ^a   Verlinden, Bert ^b   De Wolf, Ingrid ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR DEVICES; DEVICE PARAMETERS; FOCUSED ION BEAM-SCANNING ELECTRON MICROSCOPIES; MICRO-ELECTRONIC DEVICES; ROOM TEMPERATURE; SI CHIPS; THIN WAFERS; THREE-DIMENSIONAL (3D); THROUGH SILICON VIAS;

METALLIC COMPOUNDS; MICROELECTRONICS; MOS DEVICES; PHOTODEGRADATION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SEMICONDUCTOR GROWTH; SILICON; SILICON OXIDES; THREE DIMENSIONAL; TRANSMISSION ELECTRON MICROSCOPY;

SILICON WAFERS;

EID: 74249115995     PISSN: 10990062     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.3269603     Document Type: Article

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