-
1
-
-
84976728253
-
Avoiding conflict misses dynamically in large direct-mapped caches
-
B. Bershad, D. Lee, T. Romer, and B. Chen. Avoiding conflict misses dynamically in large direct-mapped caches. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 158-170, 1994.
-
(1994)
Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 158-170
-
-
Bershad, B.1
Lee, D.2
Romer, T.3
Chen, B.4
-
3
-
-
0030260286
-
Compiler-directed page coloring for multiprocessors
-
E. Bugnion, J. M. Anderson, T. C. Mowry, M. Rosenblum, and M. S. Lam. Compiler-directed page coloring for multiprocessors. In Proceedings of the seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 244-255, 1996.
-
(1996)
Proceedings of the seventh International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 244-255
-
-
Bugnion, E.1
Anderson, J.M.2
Mowry, T.C.3
Rosenblum, M.4
Lam, M.S.5
-
7
-
-
74049138489
-
-
Intel Corporation. Inside intel core microarchitecture. ftp://download.intel.com/technology/architecture/ new-architecture-06.pdf.
-
Intel Corporation. Inside intel core microarchitecture. ftp://download.intel.com/technology/architecture/ new-architecture-06.pdf.
-
-
-
-
8
-
-
3042669130
-
Ibm power5 chip: A dual-core multithreaded processor
-
R. N. Kalla, B. Sinharoy, and J. M. Tendler. Ibm power5 chip: A dual-core multithreaded processor. IEEE Micro, 24(2):40-47, 2004.
-
(2004)
IEEE Micro
, vol.24
, Issue.2
, pp. 40-47
-
-
Kalla, R.N.1
Sinharoy, B.2
Tendler, J.M.3
-
9
-
-
84976736383
-
Page placement algorithms for large real-indexed caches
-
R. E. Kessler and M. D. Hill. Page placement algorithms for large real-indexed caches. ACM Trans. Comput. Syst., 10(4):338-359, 1992.
-
(1992)
ACM Trans. Comput. Syst
, vol.10
, Issue.4
, pp. 338-359
-
-
Kessler, R.E.1
Hill, M.D.2
-
11
-
-
20344374162
-
Niagara: A 32-way multithreaded sparc processor
-
P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded sparc processor. IEEE Micro, 25(2):21-29, 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 21-29
-
-
Kongetira, P.1
Aingaran, K.2
Olukotun, K.3
-
13
-
-
57749186047
-
Gaining insights into multi-core cache partitioning: Bridging the gap between simulation and real systems
-
J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. Gaining insights into multi-core cache partitioning: Bridging the gap between simulation and real systems. In Proceedings of the 14th International Symposium on High-Performance Computer Architecture, pages 367-278, 2008.
-
(2008)
Proceedings of the 14th International Symposium on High-Performance Computer Architecture
, pp. 367-278
-
-
Lin, J.1
Lu, Q.2
Ding, X.3
Zhang, Z.4
Zhang, X.5
Sadayappan, P.6
-
14
-
-
0035511103
-
Improving performance of large physically indexed caches by decoupling memory addresses from cache addresses
-
R. Min and Y. Hu. Improving performance of large physically indexed caches by decoupling memory addresses from cache addresses. IEEE Trans. Comput., 50(11):1191-1201, 2001.
-
(2001)
IEEE Trans. Comput
, vol.50
, Issue.11
, pp. 1191-1201
-
-
Min, R.1
Hu, Y.2
-
16
-
-
34548042910
-
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
-
M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Proceedings of the 39th International Symposium on Microarchitecture, pages 423-432, 2006.
-
(2006)
Proceedings of the 39th International Symposium on Microarchitecture
, pp. 423-432
-
-
Qureshi, M.K.1
Patt, Y.N.2
-
19
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 45-57, 2002.
-
(2002)
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 45-57
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
20
-
-
1642371317
-
Dynamic partitioning of shared cache memory
-
G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. The Journal of Supercomputing, 28(1):7-26, 2004.
-
(2004)
The Journal of Supercomputing
, vol.28
, Issue.1
, pp. 7-26
-
-
Suh, G.E.1
Rudolph, L.2
Devadas, S.3
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