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Volumn , Issue , 2009, Pages

Enabling software management for multicore caches with a lightweight hardware support

Author keywords

Cache management; Multicore; Shared cache

Indexed keywords

CACHE MANAGEMENT; CACHE MANAGEMENT POLICIES; CACHE PARTITIONING; COMMODITY PROCESSORS; CORE SYSTEMS; HARDWARE SOLUTIONS; HARDWARE SUPPORTS; MULTI CORE; MULTI-CORE PROCESSOR; NON-TRIVIAL; SHARED CACHE; SOFTWARE MANAGEMENT;

EID: 74049158610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1654059.1654074     Document Type: Conference Paper
Times cited : (30)

References (22)
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    • Intel Corporation. Inside intel core microarchitecture. ftp://download.intel.com/technology/architecture/ new-architecture-06.pdf.
  • 8
    • 3042669130 scopus 로고    scopus 로고
    • Ibm power5 chip: A dual-core multithreaded processor
    • R. N. Kalla, B. Sinharoy, and J. M. Tendler. Ibm power5 chip: A dual-core multithreaded processor. IEEE Micro, 24(2):40-47, 2004.
    • (2004) IEEE Micro , vol.24 , Issue.2 , pp. 40-47
    • Kalla, R.N.1    Sinharoy, B.2    Tendler, J.M.3
  • 9
    • 84976736383 scopus 로고
    • Page placement algorithms for large real-indexed caches
    • R. E. Kessler and M. D. Hill. Page placement algorithms for large real-indexed caches. ACM Trans. Comput. Syst., 10(4):338-359, 1992.
    • (1992) ACM Trans. Comput. Syst , vol.10 , Issue.4 , pp. 338-359
    • Kessler, R.E.1    Hill, M.D.2
  • 11
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded sparc processor
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded sparc processor. IEEE Micro, 25(2):21-29, 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 14
    • 0035511103 scopus 로고    scopus 로고
    • Improving performance of large physically indexed caches by decoupling memory addresses from cache addresses
    • R. Min and Y. Hu. Improving performance of large physically indexed caches by decoupling memory addresses from cache addresses. IEEE Trans. Comput., 50(11):1191-1201, 2001.
    • (2001) IEEE Trans. Comput , vol.50 , Issue.11 , pp. 1191-1201
    • Min, R.1    Hu, Y.2
  • 16
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    • Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
    • M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Proceedings of the 39th International Symposium on Microarchitecture, pages 423-432, 2006.
    • (2006) Proceedings of the 39th International Symposium on Microarchitecture , pp. 423-432
    • Qureshi, M.K.1    Patt, Y.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.