Causality based generation of directed test cases

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 503-508

  Saxena, Nina ^a   Abraham, Jacob ^a   Saha, Avijit ^b  

^a The University of Texas at Austin   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN VERIFICATION; RANDOM TESTS; TEST CASE;

COMPUTER AIDED DESIGN; TESTING;

AUTOMATIC TEST PATTERN GENERATION;

EID: 73249145591     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368771     Document Type: Conference Paper

References (7)

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2. W. Canfield, E. A. Emerson and A. Saha, "Checking Formal Specifications Under Simulation", IEEE International Conference on Computer Design, October 1997.
3. Y. V. Hoskote, J. A. Abraham and D. S. Fussell, "Automated Verification of Temporal Properties Specified as State Machines in VHDL", Proceedings Fifth Great Lakes Symposium on VLSI, March 1995.
4. Y. Hoskote, J. Abraham, D. Fussell and J. Moondanos, "Automatic Verication of Implementations of Large Circuits Against HDL Specifications" , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, March 1997.
5. D. Moundanos, J. Abraham and Y. Hoskote, "A Unified Framework for Design Validation and Manufacturing Test", Proceedings IEEE International Test Conference, October 1996.
6. S. P. Rajan and Masahiro Fujita, "Integration of High-level Modeling, Formal Verification, and High-level Synthesis in ATM Switch Design", IEEE International Conference on VLSI Design, January 1998.
7. N. Saxena, J. Baumgartner, A. Saha and J. Abraham, "To Model Check Or Not To Model Check", ICCD, October 1998.