Automated verification of temporal properties specified as state machines in VHDL

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1995, Pages 100-105

  Hoskote, Yatin V ^a   Abraham, Jacob A ^a   Fussell, Donald S ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTATIONAL COMPLEXITY; LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SEQUENTIAL MACHINES; STATE ASSIGNMENT;

AUTOMATED VERIFICATION; TEMPORAL PROPERTIES; VIPER MICROPROCESSOR;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0029213613     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)