Integration of high-level modeling, formal verification, and high-level synthesis in ATM Switch design

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 552-557

  Rajan, Sreeranga P ^a   Fujita, Masahiro ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; MATHEMATICAL MODELS; THEOREM PROVING;

FORMAL VERIFICATION; HIGH LEVEL MODELING; HIGH LEVEL SYNTHESIS;

SWITCHING NETWORKS;

EID: 0031655863     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)