Unified framework for design validation and manufacturing test

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 875-884

  Moundanos, Dinos ^a   Abraham, Jacob A ^a   Hoskote, Yatin V ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; ELECTRIC FAULT CURRENTS; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; VECTORS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); VERIFICATION VECTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0030398537     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)