Automatic verification of implementations of large circuits against HDL specifications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 3, 1997, Pages 217-228

  Hoskote, Yatin V ^a   Abraham, Jacob A ^b   Fussell, Donald S ^a   Moondanos, John ^a  

^a INTEL CORPORATION   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Containment; Equivalence; Hardware description languages; Sequential circuits; Verification

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DECISION TABLES; FINITE AUTOMATA; LOGIC GATES; OPTIMIZATION; SET THEORY;

BINARY DECISION DIAGRAMS (BDD); FINITE STATE MACHINES (FSM);

SEQUENTIAL CIRCUITS;

EID: 0031100802     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.594828     Document Type: Article

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