Tolerance to small delay defects by adaptive clock stretching

Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium

Volumn , Issue , 2007, Pages 244-249

  Ghosh, Swaroop ^a   NDai, Patrick ^a   Bhunia, Swarup ^b   Roy, Kaushik ^a  

^a Purdue University   (United States)

^b Case Western Reserve University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; BENCHMARKING; CLOCKS; DEFECTS; DIES; EIGENVALUES AND EIGENFUNCTIONS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT TESTING; PIPELINES; SULFATE MINERALS; TIMING CIRCUITS;

(+ MOD 2N) OPERATION; BRIDGING DEFECTS; CIRCUIT DELAYS; CLOCK GATING; CLOCK PERIODS; CLOCK STRETCHING; COMPUTATION TIME; CONVENTIONAL DESIGNS; CRITICAL PATHS; DELAY DEFECTS; DELAY SPREAD (DS); DELAY VARIATIONS; DUAL VTH; GOOD YIELDS; HANDSHAKING; IN ORDER; INTERNATIONAL (CO); LOW-POWER DESIGNS; MANUFACTURING DEFECTS; MCNC BENCHMARKS; NANOSCALED; NEW DESIGN; NON-LINEAR; ON LINE TESTING; PARAMETER FLUCTUATIONS; PARAMETRIC VARIATIONS; PARAMETRIC YIELD; PATH DELAY (PD); PERFORMANCE ANALYSES; SIMPLESCALAR; SIMULATION RESULTS; TIMING SLACK; VOLTAGE-SCALING;

NETWORKS (CIRCUITS);

EID: 46749135215     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2007.67     Document Type: Conference Paper

References (14)

1. th, and sizing, DAC 2004.
2. S. Borkar et al., Design and reliability challenges in nanometer technologies, DAC, 2004.
3. X. Bai et al., Uncertainty-aware circuit optimization, DAC, 2002.
4. S. Ghosh et al., A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation, ICCAD, 2006.
5. L. Benini et al., Telescopic units: Increasing the average throughput of pipelined designs by adaptive latency control, DAC, 1997.
6. L. Lavagno et al. Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool, DAC, 1995.
7. B. C. Paul et al., Novel sizing algorithm for yield improvement under process variation in nanometer, DAC, 2004.
8. K. Kang et al., Statistical timing analysis using levelized covariance propagation, DATE, 2005.
9. Synopsys Design Compiler, www.synopsys.com.
10. BPTM 70nm: Berkeley predictive technology model.
11. J. Hennessy and D. Patterson, Computer architecture: a quantitative approach, Morgan Kaufmann Pub. Inc., 1990.
12. T. Austin et al., Simplescalar: An infrastructure for computer system modeling. Computer, 2002.
13. L. Carloni et al., Theory of latency-insensitive design, TCAD, 2001.
14. J. Cortadella et al., Synthesis of synchronous elastic architectures, DAC, 2006.