A 1 MHz bandwidth, 6 GHz 0.18 μm CMOS type-I δσ fractional-N synthesizer for WiMAX applications

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3244-3252

  Hedayati, Hiva ^a   Khalil, Waleed ^b   Bakkaloglu, Bertan ^c  

^a MARVELL SEMICONDUCTOR INC   (United States)

^b The Ohio State University   (United States)

^c Arizona State University   (United States)

Author keywords

Fractional N synthesizer; Phase locked loop (PLL); Quantization noise; Sigma delta modulator; Wideband

Indexed keywords

CHARGE-PUMP; CMOS TECHNOLOGY; DISCRETE-TIME; FRACTIONAL-N; FRACTIONAL-N SYNTHESIZER; IN-BAND; IN-BAND PHASE NOISE; METAL LAYER; OUT-OF-BAND; PHASE ERROR; POWER SUPPLY; QUANTIZATION NOISE; SETTLING TIME; SIGMA DELTA MODULATOR; WIDE-BAND; WORST CASE;

CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL INTEGRATED CIRCUITS; MODULATION; PHASE LOCKED LOOPS; PHASE NOISE; WIMAX;

MODULATORS;

EID: 72949121092     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2032713     Document Type: Conference Paper

References (14)

1. H. Hedayati, B. Bakkaloglu, and W. Khalil, "A 1 MHz bandwidth type-Iδσ-fractional-N synthesizer forWiMAXapplications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, p. 310.
2. B. Bisla, R. Eline, and L. M. Franca-Neto, "RF system and circuit challenges for WiMAXs," Intel Technol. J., vol.08, no.03, pp. 189-200, Aug. 2004.
3. T. Pollet, M. Van Blade, and M. Moeneclaey, "BER sensitivity of OFDM systems to carrier frequency offset and Wiener phase noise," IEEE Trans. Commun., vol.43, pp. 191-193, Feb. 1995.
4. H. Hedayati, B. Bakkaloglu, and W. Khalil, "Closed loop nonlinear modeling of wideband σδ fractional-N frequency synthesizers," IEEE Trans. Microw. Theory Tech., vol.54, no.10, pp. 3654-3663, Oct. 2006.
5. M. S. J. Steyaert, B. De Muer, P. Leroux, M. Borremans, and K. Mertens, "Low-voltage low-power CMOS-RF transceiver design," IEEE Trans. Microw. Theory Tech., vol.50, no.1, pp. 281-287, Jan. 2002.
6. S. E. Meninger and M. H. Perrott, "A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.50, no.11, pp. 839-849, Nov. 2003.
7. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-Sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol.28, no.5, pp. 53-59, May 1993.
8. W. Rhee, B.-S. Song, and A. Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-bit third-order σδ modulator," IEEE J. Solid-State Circuits, vol.35, no.8, pp. 1453-1460, Aug. 2000.
9. B. De Muer and M. S. J. Steyaert, "A CMOS monolithic δσ -controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuits, vol.37, no.7, pp. 835-844, Jul. 2002.
10. T. A. D. Riley, N. M. Filiol, D. Qinghong, and J. Kostamovaara, "Techniques for in-band phase noise reduction in σδ synthesizers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.50, no.11, pp. 794-803, Nov. 2003.
11. K. J.Wang, A. Swaminathan, and I. Galton, "Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL," IEEE J. Solid-State Circuits, vol.43, no.12, pp. 2787-2797, Dec. 2008.
12. M. Gupta and B.-S. Song, "A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 2842-2851, Dec. 2006.
13. E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-KHz bandwidth σδ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications," IEEE J. Solid-State Circuits, vol.39, no.9, pp. 1446-1454, Sep. 2004.
14. S. T. Lee, S. J. Fang, D. J. Allstot, A. Bellaouar, A. R. Fridi, and P. A. Fontaine, "A quad-band GSM-GPRS transmitter with digital auto-calibration," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2200-2214, Dec. 2004.