Full simulation coverage for SystemC transaction-level models of systems-on-a-chip

Formal Methods in System Design

Volumn 35, Issue 2, 2009, Pages 152-189

  Helmstetter, C ^a,c   Maraninchi, F ^a   Maillet Contoz, L ^b  

^a VERIMAG   (France)

^b STMICROELECTRONICS   (France)

^c INRIA Grenoble   (France)

Author keywords

Dynamic partial order reduction; Loose timing; Runtime verification; Scheduling; Simulation; System on a Chip; Test coverage; Translational modeling

Indexed keywords

BUS ARBITER; CONSTRAINT SOLVING; HARDWARE PLATFORM; LOCAL ERROR; ON DYNAMICS; PARTIAL ORDER REDUCTIONS; RUN-TIME VERIFICATION; RUNTIMES; SCHEDULING MECHANISM; SCHEDULING SIMULATION; SIMULATION ENGINE; SIMULATION TIME; SPECIFIC VALUES; SYSTEM-ON-A-CHIP; SYSTEMC; SYSTEMS-ON-A-CHIP; TEST SCENARIO; TIME INTERVAL; TIMING ANNOTATIONS; TRANSACTION LEVEL MODELING; TRANSACTION-LEVEL MODEL; VIRTUAL PROTOTYPE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DISPENSERS; EMBEDDED SOFTWARE; LARGE SCALE SYSTEMS; SCHEDULING; SIGNAL ENCODING; TEST FACILITIES; THERMOLUMINESCENCE; TIME MEASUREMENT;

SIMULATORS;

EID: 72249106863     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10703-009-0075-z     Document Type: Article

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