Formal verification of SystemC designs using a petri-net based representation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Karlsson, Daniel ^a   Eles, Petru ^a   Peng, Zebo ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MATHEMATICAL MODELS; MODEL CHECKING; PETRI NETS; SYSTEMS ANALYSIS;

SYSTEMC DESIGNS; TIMED TEMPORAL LOGIC; TRANSACTION LEVEL;

TEMPORAL LOGIC;

EID: 34047148417     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244076     Document Type: Conference Paper

References (11)

1. M. Baird, "SystemC 2.0.1 Language Reference Manual", Open SystemC Initiative, 2003
2. J. Ruf, D.W. Hoffmann, T. Kröpf et al., "Simulation-guided Property Checking based on Multi-valued ar-automata", Proc. DATE, 2001, pp. 742-748
3. F. Ferrandi, M. Rendine, D. Scuito, "Functional Verification for SystemC Descriptions using Constraint Solving", Proc. DATE, 2002, pp. 744-751
4. D. Große, R. Drechsler, "Formal Verification of LTL Formulas for SystemC Designs", Proc. ISCAS, 2003, pp. 245-248
5. D. Große, R. Drechsler, "CheckSyC: An Efficient Properly Checker for RTL SystemC Designs", Proc. ISCAS, 2005, pp. 4167-4170
6. D. Kroening, N. Sharygina, "Formal Verification of SystemC by Automatic Hardware/Software Partitioning", Proc. MEMOCODE, 2005, pp. 101-110
7. L.A. Cortés, P. Eies, Z. Peng, "Verification of Embedded Systems using a Petri Net based Representation", Proc. ISSS, 2000, pp. 149-155
8. E.M. Clarke, O. Grumberg, D.A. Peled, Model Checking, MIT Press, 1999
9. R. Alur, C. Courcoubetis, et al., "Model-checking for Real-time Systems", Proc. Logic in Computer Science, 1990, pp. 414-425
10. UPPAAL hompage, http://www.uppaal.com/
11. A. Rose, S. Swan, J. Pierce et al., "Transaction Level Modeling in SystemC", Open SystemC Initiative, 2005