Partial order reduction for scalable testing of SystemC TLM designs

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 936-941

  Kundu, Sudipta ^a   Ganai, Malay ^b   Gupta, Rajesh ^a  

^a NEC Labs America ^*

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Partial order reduction; Simulation; Testing; Verification

Indexed keywords

PARTIAL-ORDER REDUCTION; SIMULATION; SYSTEMC; TESTING; VERIFICATION;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; INFORMATION THEORY;

LOGIC DESIGN;

EID: 51549111647     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555954     Document Type: Conference Paper

References (22)

1. Edison Design Group (EDG) C/C++ Front End, 1992. www.edg.com.
2. IEEE Standard 1666 SystemC Language Reference Manual, 2005. www.systemc.org.
3. ST Microelectronics Transaction Accurate Communication (TAC) platform, 2005. www.greensocs.com/TACPackage.
4. T. Ball, R. Majumdar, T. Millstein, and S. Rajamani. Automatic predicate abstraction of C programs. In SIGPLAN Conference on PLDI, 2001.
5. L. Cai and D. Gajski. Transaction Level Modeling: an overview. In Proceedings of CODES+ISSS, 2003.
6. M. Dwyer and J. Hatcliff. Slicing software for model construction. In ACM Workshop on PEPM, 1999.
7. C. Flanagan and P. Godefroid. Dynamic partial-order reduction for model checking software. In Proceedings of POPL, 2005.
8. M. Girkar and C. D. Polychronopoulos. Automatic extraction of functional parallelism from ordinary programs. IEEE Trans. Parallel Distrib. Syst., 1992.
9. P. Godefroid. Partial-order methods for the verification of concurrent systems: an approach to the state-explosion problem. PhD thesis, Univerite De Liege, 1995.
10. P. Godefroid. Model checking for programming languages using VeriSoft. In Proceedings of POPL, 1997.
11. D. Grobe, R. Ebendt, and R. Drechsler. Improvements for constraint solving in the SystemC verification library. In Proceedings of GLSVLSI, 2007.
12. T. Grötker, S. Liao, G. Martin, and S. Swan. System Design with SystemC. Kluwer Academic Publishers, 2002.
13. A. Habibi and S. Tahar. Design for verification of SystemC Transaction Level Models. In Proceedings of DATE, 2005.
14. C. Helmstetter, F. Maraninchi, L. Maillet-Contoz, and M. Moy. Automatic generation of schedulings for improving the test coverage of Systems-on-a-Chip. In Proceedings of FMCAD, 2006.
15. G. J. Holzmann. The model checker SPIN. Software Engineering, 1997.
16. D. Kroening and N. Sharygina. Formal verification of SystemC by automatic hardware/software partitioning. In Proceedings of MEMOCODE, 2005.
17. S. Meftali, J. Vennin, and J.-L. Dekeyser. A fast SystemC simulation methodology fo Multi-Level IP/SoC design. In IFIP Intl. Workshop on IP Based SoC Design, 2003.
18. M. Moy, Maraninchi, and Maillet-Contoz. Lussy: A toolbox for the analysis of Systems-on-a-Chip at the Transactional Level. In Proceedings of ACSD, 2005.
19. A. Sen and V. K. Garg. Formal verification of simulation traces using computation slicing. IEEE Transactions on Computers, 2007.
20. R. Shyamasundar, F. Doucet, R. Gupta, and I. Kruger. Compositional reactive semantics of SystemC and verification with RuleBase. In Proceedings of the GM R&D Workshop, 2007.
21. S. Swan. SystemC Transaction Level Models and RTL verification. In Proceedings of DAC, 2006.
22. M. Y. Vardi. Formal techniques for SystemC verification. In Proceedings of DAC, 2007.