Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

Volumn , Issue , 2009, Pages 325-334

  Rana, Vincenzo ^a   Murali, Srinivasan ^b   Atienza, David ^b   Santambrogio, Marco Domenico ^c   Benini, Luca ^d   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

^b EPFL   (Switzerland)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Adaptable computing; FPGAs; Mapping algorithms; Reconfigurable computing

Indexed keywords

APPLICATION EXECUTION; DESIGN AUTOMATIONS; DESIGN OPTIMIZATION; FLOW FEATURES; HARDWARE COMPONENTS; MAPPING ALGORITHMS; MULTI-STAGE; MULTI-STAGE OPTIMIZATION; MULTIPLE APPLICATIONS; NOVEL DESIGN; RE-CONFIGURABLE; RECONFIGURABILITY; RECONFIGURABLE COMPUTING; RECONFIGURATION ALGORITHM; RECONFIGURATION COSTS; RECONFIGURATION LATENCY; RECONFIGURATION OVERHEAD; RUN TIME RECONFIGURATION; RUNTIMES; SYSTEM-ON-CHIP PLATFORMS; TRAFFIC FLOW;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; COMPUTER AIDED DESIGN; CONFORMAL MAPPING; COST REDUCTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; TRAFFIC SURVEYS;

EMBEDDED SYSTEMS;

EID: 72149088506     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629435.1629480     Document Type: Conference Paper

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