Multi-layer floorplanning on a sequence of reconfigurable designs

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 605-612

  Singhal, Love ^a   Bozorgzadeh, Elaheh ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK PERIODS; DESIGN QUALITY; DEVICE AREA; FIELD PROGRAMMABLE LOGIC (FPL); FLOOR PLANNING; FLOOR-PLANNING; FLOORPLANNER; FLOORPLANS; FPGA DESIGNS; FUTURE DESIGNS; HIGH QUALITY (HQ); IN ORDER; INTERNATIONAL CONFERENCES; MINIMAL AREA; MULTILAYER (ML); PARTIAL DYNAMIC RECONFIGURATION; PARTIAL RECONFIGURATION; PLACE AND ROUTE; RECONFIGURABLE DESIGNS; RECONFIGURATION OVERHEAD; RUN TIME; SUB-DESIGNS; WIRE LENGTHS;

DYNAMIC MODELS; FUZZY LOGIC; REUSABILITY;

INTEGRATED CIRCUIT LAYOUT;

EID: 46249130833     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311273     Document Type: Conference Paper

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