Optimal loop parallelization for maximizing iteration-level parallelism

Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

Volumn , Issue , 2009, Pages 67-76

  Liu, Duo ^a   Shao, Zili ^a   Wang, Meng ^a   Guo, Minyi ^b   Xue, Jingling ^c  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

^c UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

Data dependence graph; Iteration level parallelism; Loop parallelization; Loop transformation; Retiming

Indexed keywords

DATA DEPENDENCE GRAPHS; EDGE WEIGHTS; GRAPH OPTIMIZATION; LOOP TRANSFORMATION; NUMBER OF ITERATIONS; ON-CHIP MULTIPROCESSOR; OPEN PROBLEMS; OPTIMAL ALGORITHM; OPTIMAL CODES; PARALLELIZATIONS; RETIMING; THREE STAGES; TWO PHASIS;

ALGORITHMS; GRAPH THEORY; OPTIMAL SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS;

EMBEDDED SYSTEMS;

EID: 72049107238     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629395.1629407     Document Type: Conference Paper

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