Evaluating the performance of a chaos genetic algorithm for solving the network on chip mapping problem

Proceedings - 12th IEEE International Conference on Computational Science and Engineering, CSE 2009

Volumn 2, Issue , 2009, Pages 366-373

  Moein darbari, Fahime ^a   Khademzadeh, Ahmad ^b   Gharooni fard, Golnar ^a  

^a ISLAMIC AZAD UNIVERSITY   (Iran)

^b Research Center   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

CHAOS GENETIC ALGORITHM; CHAOTIC MAP; CHAOTIC SEQUENCE; IN-NETWORK; MAPPING PROBLEM; MESH-BASED NOC; NETWORK-ON-CHIP MAPPING PROBLEMS; NOVEL TECHNIQUES; PERFORMANCE INDICES; SINGLE CHIPS; TASK GRAPH;

BUILDING MATERIALS; ELECTRIC NETWORK TOPOLOGY; GENETIC ALGORITHMS; MAPPING; MICROPROCESSOR CHIPS; QUALITY OF SERVICE; RANDOM PROCESSES; UBIQUITOUS COMPUTING;

CHAOTIC SYSTEMS;

EID: 70749136234     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSE.2009.321     Document Type: Conference Paper

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