A sharable built-in self-repair for semiconductor memories with 2-D redundancy scheme

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2007, Pages 331-339

  Bahl, Swapnil ^a  

^a STMicroelectronics Marketing Pvt Ltd India   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BIRA ALGORITHM; BUILT-IN REDUNDANCY ANALYSIS; BUILT-IN SELF-REPAIR; BUILTIN SELF-TEST (BIST); MEMORY REPAIR; PROCESS MATURITY; REDUNDANCY SCHEME; SEMICONDUCTOR MEMORY;

ALGORITHMS; BUILT-IN SELF TEST; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; PROGRAMMABLE LOGIC CONTROLLERS; REDUNDANCY; SEMICONDUCTOR STORAGE;

REPAIR;

EID: 70549105064     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2007.28     Document Type: Conference Paper

References (14)

1. .ITRS survey 2000.
2. .D.K.Bhavsar."An algorithm for row-column repair of RAMs and its implementation in the Alpha 21264", Proc.IEEE Int.Test Conf., ITC'99,1999, pp.311-318.
3. .W.K.Fuchs, "Efficient Spare Allocation for Reconfigurable Arrays", IEEE Design &Test of Computers, 1987, Vol 4, pp.24-31.
4. .O.H.Ibarra and S.M.Sohn, "On Mapping Systolic Algorithms onto the Hypercube," IEEE Trans.Parallel and Distrubuted Systems, vol.1, 1990, pp.48-63.
5. .Kim H.C., Yi D.S., Park J.Y., Cho C.H., "A BISR (Built-In Self-Repair) circuit for embedded memory with multiple redundancies", 1999 IEEE International Conference on VLSI and CAD, Oct.26-27, 1999, Seoul, Korea, pp 602-605.
6. .T.Kawagoe, J.Ohtani, M.Niiro et al, "A built-in self-repair analyzer (CRESTA) for embedded DRAMs", Proc.IEEE Int.Test Conf., ITC'00, 2000, pp.567-574.
7. .V.Vardanian, Y.Zorian, "An approach for evaluation of redundancy analysis algorithms", Proc.IEEE Int.workshop on Memory Tech., Design and Testing, MTDT'01, 2001.
8. .S.Shoukourian, V.Vardanian, Y.Zorian, "A methodology for design and evaluation of redundancy allocation algorithm".Proc.22nd IEEE VLSI Test Symposium (VTS 2004).
9. .N.Hasan and C.L.Liu, "Minimum fault coverage in reconfigurable arrays," IEEE Fault-Tolerant Computing Symposium, June 1988, pp.348-353.
10. .W.K.Huang, Y.N.Shen, and F.Lombardi, "New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement", IEEE Trans.on Computer-Aided Design, March 1990, pp.323-328.
11. .Hung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, and Sy-Yen Kuo, "An Efficient Perfect Algorithm for Memory Repair Problems", Proceedings of the 19th IEEE International Symposium on Defect &Fault Tolerance, DFT 04.
12. .Junichi Hirase, "Yield increase of VLSI after redundancy- repairing", Test Symposium, 2001.Proceedings.10th Asian.
13. Wey and Lombardi, "On the repair of redundant RAM's" Proc IEEE Transactions on computer aided Design 1987.
14. Swapnil Bahl and Balwant Singh, "A novel method for silicon configurable Test Flow and Algorithms for Testing,different Types of Embedded Memories through a shared controller", IEEE Memory Technology, Design and Test,MTDT'04 2004.