A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2004, Pages 78-83

  Bahl, Swapnil ^a   Singh, Balwant ^a  

^a STMicroelectronics Marketing Pvt Ltd India   (India)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED MEMORIES; SYSTEM ON CHIPS (SOC); TEST FLOW; TIME TO MARKET;

ALGORITHMS; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; PROGRAM DEBUGGING; ROM; SILICON; STATIC RANDOM ACCESS STORAGE;

EMBEDDED SYSTEMS;

EID: 10044265435     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2004.1327988     Document Type: Conference Paper

References (10)

1. ITRS survey 2000.
2. G. E. Moore. Progress in Digital Integrated Electronics. In Proc. IEEE IEDM, pages 11-13, 1975.
3. K. K. Saluja, S. H. Sng, and K. Kinoshita, "Built-in self-testing RAM: A practical alternative", IEEE Design & Test of Computers, vol. 4, no. 1, pp. 42-51, Feb 1987.
4. A.J. van de Goor. Testing Semiconductor Memories: Theory and Practice. John Wiley and Sons, USA 1991.
5. B.F. Cockbum and Y.F. Nicole Sat. "Synthesized Transparent BIST for Detecting Scrambled Pattern Sensitive Faults in RAM". In Proc. Int. Test Conf., pages 23-32, 1995.
6. R. Dekker, F. Beenker, and H. Tijseen, "A Realistic Fault Models and Test Algorithms for Static Random Access Memories", IEEE trans. On CAD, Vol 9, No. 6, pp. 567-572, June 1990.
7. S. Hamdioui, and A.J. van de Goor, "An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests", In Proc. Of the Ninth Asian Test Symposium, pp. 131-138, 2000.
8. J. Zhao, S. Irrinki, M. Puri and F. Lombardi, "Detection of Inter-port Faults in Multi-Port Static Rams", In Proc. of VLSI Test Symposium, Montreal, Canada, pp. 297-302, 2000.
9. K. Zarrineh and S.J. Upadhaya. "On Programmable Memory Built-In Self Test Architectures". In Design Automation and Test in Europe, pages 708-713, March 1999.
10. IEEE Std 1149.1-1993, "Standard Test Access Port and Boundary Scan Architecture", IEEE Standards Board, USA