A methodology for design and evaluation of redundancy allocation algorithms

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 249-255

  Shoukourian, S ^a   Vardanian, V A ^a   Zorian, Y ^a  

^a Virage Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN-SELF-TEST (BIST); MEMORY ARRAYS; SELF-TEST AND REPAIR (STAR);

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SOFTWARE; STATIC RANDOM ACCESS STORAGE;

RESOURCE ALLOCATION;

EID: 3142745429     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299251     Document Type: Conference Paper

References (8)

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3. T. Kawagoe, J. Ohtani, M. Niiro et al, A built-in self-repair analyzer (CRESTA) for embedded DRAMs, Proc. ITC'2000, pp. 567-574.
4. S. Shoukourian, V. Vardanian, Y. Zorian, An approach for evaluation of redundancy analysis algorithms, Proc. MTDT 2001, pp. 51-55.
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6. V. Vardanian, G. Gabrielyan, A Tool for evaluation and comparison of redundancy allocation algorithms, for Static Random Access Memories, Proc. Int. Conference on Computer Science and Information Technologies, CSIT'2003, Yerevan, Armenia, 2003, pp. 391-394.
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8. M. Tarr, D. Boudreau, R. Murphy, Defect analysis system speeds test and repair of redundant memories, Electronics, pp. 175-179, Jan. 1984.