Using hardware transactional memory for data race detection

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Gupta, Shantanu ^a   Sultan, Florin ^b   Cadambi, Srihari ^b   Ivancic F ^b   Rötteler, Martin ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA COST; CONFLICT DETECTION; DATA RACE DETECTION; DATA RACES; DYNAMIC DATA; HARDWARE SUPPORTS; MULTI-CORE PROCESSOR; MULTITHREADED SOFTWARES; PARALLEL APPLICATION; PROOF OF CONCEPT; SPECIALIZED HARDWARE; TRANSACTIONAL MEMORY;

DISTRIBUTED PARAMETER NETWORKS; PROGRAM DEBUGGING; STORAGE ALLOCATION (COMPUTER);

HARDWARE;

EID: 70450056331     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161006     Document Type: Conference Paper

References (32)

1. Helgrind: a thread error detector (http://valgrind.org/docs/manual/hg- manual.html).
2. C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded Transactional Memory. In Proc. 11th Symposium on High-Performance Computer Architecture, 2005.
3. S. Chen, M. Kozuch, T. Strigkos, B. Falsafi, P. B. Gibbons,T. C. Mowry, V. Ramachandran, O. Ruwase, M. Ryan, and E. Vlachos. Flexible hardware acceleration for instructiongrain program monitoring. SIGARCH Comput. Archit. News, 36(3):377-388, 2008.
4. P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid Transactional Memory. In Architectural Support for Programming Languages and Operating Systems, 2006.
5. C. Fidge. Logical Time in Distributed Computing Systems. Computer, 24(8):28-33, 1991.
6. S. Gupta, F. Sultan, S. Cadambi, F. Ivancǎić, and M. Roetteler. RaceTM: Detecting Data Races Using Transactional Memory. In Symposium on Parallelism in Algorithms and Architectures, 2008. (Brief announcement).
7. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis,B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In Proc. 31st International Symposium on Computer Architecture, Jun 2004.
8. T. Harris and K. Fraser. Language Support for Lightweight Transactions. In Proc. 18th Conference on Object-orientedprograming, systems, languages, and applications, 2003.
9. M. Herlihy, V. Luchangco, M. Moir, and I. William N. Scherer. Software Transactional Memory for Dynamic-Sized Data Structures. In Symposium on Principles of Distributed Computing, July 2003.
10. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In Proc. 20th International Symposium on Computer Architecture, May 1993.
11. M. Hind. Pointer analysis: Haven't we solved this problem yet? In Workshop on Program Analysis For Software Tools and Engineering (PASTE), 2001.
12. A. H. Karp and J.-F. C. Collard. Synchronization of Threads in a Multithreaded Computer Program. U.S. Patent Application Publication Pub No. US 2005/0283789, Dec. 2005.
13. L. Lamport. Time, Clocks, and the Ordering of Events in a Distributed System. Comm. ACM, 21(7):558-565, 1978.
14. S. Lu, S. Park, E. Seo, and Y. Zhou. Learning from mistakes - A Comprehensive Study on Real World Concurrency Bug Characteristics. In Proc. 13th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2008.
15. F. Mattern. Virtual Time and Global States of Distributed Systems. In Proc. Intl. Workshop on Parallel and Distributed Algorithms. 1988.
16. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees. In Proc. 34th International Symposium on Computer Architecture, 2007.
17. K. Moore, J. Bobba, M. Moravan, M. Hill, and D.Wood. LogTM: log-based transactional memory. In Proc. 12th Symposium on High-Performance Computer Architecture, Feb. 2006.
18. R. O'Callahan and J.-D. Choi. Hybrid dynamic data race detection. In Principles and practice of parallel programming, 2003.
19. D. Perkovic and P. Keleher. Online data-race detection via coherency guarantees. In Proc. 2nd Symp. on Operating Systems Design and Implementation (OSDI'96), 1996.
20. E. Pozniansky and A. Schuster. Efficient on-the-fly data race detection in multithreaded C++ programs. In Proc. Parallel and Distributed Processing Symposium, Apr. 2003.
21. M. Prvulovic. CORD: Cost-effective (and nearly overheadfree) Order-Recording and Data Race Detection. In Proc. 12th Symposium on High-Performance Computer Architecture, 2006.
22. M. Prvulovic and J. Torrellas. ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. In Symposium on Computer Architecture, 2003.
23. R. Rajwar, M. Herlihy, and K. Lai. Virtualizing Transactional Memory. In Proc. 32nd International Symposium on Computer Architecture, 2005.
24. H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, and E. Witchel. TxLinux: Using and Managing Transactional Memory in an Operating System. 2007.
25. C. J. Rossbach, D. E. Porter, O. S. Hofmann, H. E. Ramadan, A. Bhandari, and E. Witchel. MetaTM/TxLinux: Transactional Memory For An Operating System. 2007.
26. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson. Eraser: A Dynamic Data Race Detector for Multithreaded Programs. ACM Trans. Comput. Syst., 15(4):391-411, 1997.
27. N. Shavit and D. Touitou. Software Transactional Memory. In Proc. 14th Symposium on Principles of Distributed Computing, 1995.
28. M. Tremblay and S. Chaudhry. A Third-Generation 65nm 16- Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor. In Intl. Solid-State Circuits Conference, 2008.
29. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Symposium on Computer Architecture, 1995.
30. L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In sSymposium on High Performance Computer Architecture, 2007.
31. Y. Yu, T. Rodeheffer, and W. Chen. RaceTrack: Efficient Detection of Data Race Conditions via Adaptive Tracking. In Proc. 20th Symposium on Operating Systems Principles, Oct 2005.
32. P. Zhou, R. Teodorescu, and Y. Zhou. HARD: Hardware-Assisted Lockset-based Race Detection. Symposium on High Performance Computer Architecture, pages 121-132, Feb 2007.