A new method to fabricate sidewall insulation of TSV using a parylene protection layer

2009 International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2009

Volumn , Issue , 2009, Pages 60-63

  Ming, Ji ^a   Yunhui, Zhu ^a   Shenglin, Ma ^a   Xin, Sun ^a   Min, Miao ^a,b   Yufeng, Jin ^a  

^a PEKING UNIVERSITY   (China)

^b BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ELECTRICAL INTERCONNECTIONS; ETCHING PROCESS; INSULATION LAYERS; OXIDE LAYER; PARYLENE C; PARYLENES; PROTECTION LAYERS; THROUGH-SILICON-VIA;

ELECTRONICS PACKAGING; PACKAGING; SILICON COMPOUNDS; SILICON OXIDES;

ANISOTROPIC ETCHING;

EID: 70449971116     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICEPT.2009.5270793     Document Type: Conference Paper

References (6)

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3. Beica R. et al, "Advanced Metallization for 3D Integration," Proc 10th Electronics Packaging Technology Conf, Singapore, Dec. 2008, pp. 212-218.
4. Cho Byeong-Hoon, et al, "Filling of Very Fine Via Holes for Three Dimensional Packaging by Using Ionized Metal Plasma Sputtering and Electroplating," International Conf on Electronic Materials and Packaging, Daejeon, Korea, Nov. 2007, pp. 1-3.
5. Sun C. M., et al, "A novel double-side CMOS-MEMS post processing for monolithic sensor integration," Proc of 21st IEEE International Conf on Micro Electro Mechanical Systems, Tucson, AZ, Jan. 2008, pp. 90-93.
6. Ji Xu, et al, "Parylene film for sidewall passivation in SCREAM process," Science in China Series E: Technological Sciences, Vol. 52, No. 2 (2009), pp. 357-362.