Research on deep RIE-based through-si-via micromachining for 3-D system-in-package integration

4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2009

Volumn , Issue , 2009, Pages 90-93

  Miao, Min ^a,b   Jin, Yufeng ^a   Liao, Hongguang ^a   Zhao, Liwei ^a   Zhu, Yunhui ^a   Sun, Xin ^a   Guo, Yunxia ^a  

^a PEKING UNIVERSITY   (China)

^b BEIJING INFORMATION SCIENCE AND TECHNOLOGY UNIVERSITY   (China)

Author keywords

Bulk micromachining; Deep reactive ion etching (DRIE); System in package (SiP); Three dimensional integration; Through si via (TSV)

Indexed keywords

BULK MICROMACHINING; DEEP REACTIVE ION ETCHING (DRIE); SYSTEM-IN-PACKAGE (SIP); THREE DIMENSIONAL INTEGRATION; THROUGH-SI-VIA (TSV);

CELLULAR RADIO SYSTEMS; COMPOSITE MICROMECHANICS; CONSUMER ELECTRONICS; ELECTRON BEAM LITHOGRAPHY; ELECTRONIC EQUIPMENT MANUFACTURE; EVOLUTIONARY ALGORITHMS; INTERNET PROTOCOLS; MICROMACHINING; MODELS; SYSTEMS ANALYSIS; THREE DIMENSIONAL;

REACTIVE ION ETCHING;

EID: 70349678323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEMS.2009.5068533     Document Type: Conference Paper

References (6)

1. S. Pozder; R. Chatterjee, A. Jain, et al, "Progress of 3D Integration Technologies and 3D Interconnects", IEEE International Interconnect Technology Conference, Volume A, June 2007, pp. 213 - 215
2. O. Aharon, L.Gal, Y. Nemirovsky, "Hybrid Approach for RF MEMS Devices", Proceedings of the IEEE COMCAS 2008, 2008.6, Tel-Aviv, Israel.
3. L. Schaper, et al, "Architectural Implications and Process Development of 3-D VLSI Z-Axis InterconnectsUsing Through Silicon Vias", IEEE Transactions on Advanced Package, Vol. 28, No.3, August, 2005, pp. 355-365.
4. Zhou R., Zhang H., Hao Y. and Wang Y., "The simulation of the Bosch process with string-cell hybrid Method", Journal of Micromechanics and Microengineering, volume 14, issue 7 (2004), pages 851 - 858.
5. Robert Bosch Gmbh, "Challenges, developments and applications of silicon deep reactive ion etching", Microelectronic Engineering, Vol: 67 - 68 (2003), pp. 349 - 355
6. Zhou R., "The modelling, simulation and experimental verification of high aspect ratio silicon etching process techniques", Ph.D dissertation, Peking University, China, 2005.