Modeling post-techmapping and post-clustering FPGA circuit depth

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 205-211

  Das, Joydip ^a   Wilton, Steven J E ^a   Leong, Philip ^b   Luk, Wayne ^c  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^c IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; ARCHITECTURAL PARAMETERS; CLUSTER SIZES; EXPERIMENTAL APPROACHES; FPGA CIRCUITS; FPGA IMPLEMENTATIONS; LOOK UP TABLE; TECHNOLOGY MAPPING;

TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449953949     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272315     Document Type: Conference Paper

References (14)

1. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-submicron FPGAs. Kluwer Academic Publishers, 1999.
2. W. Fang and J. Rose, "Modeling FPGA routing demand in early-stage architecture development," in Field Programmable Gate Arrays, 2008. ACM/SIGDA International Symposium on, Feb. 2008, pp. 139-148.
3. A. Lam, S. Wilton, P. Leong, and W. Luk, "An analytical model describing the relationships between logic architecture and FPGA density," in Field Programmable Logic and Applications, 2008. International Conference on, Sept. 2008, pp. 221-226.
4. A. Smith, J. Das, and S.Wilton, "Wirelength modeling for homogeneous and heterogeneous FPGA architectural development," in Field Programmable Gate Arrays, 2009. ACM/SIGDA International Symposium on, Feb. 2009, pp. 181-190.
5. H. Gao, Y. Yang, X.Ma, and G. Dong, "Analysis of the effect of lut size on FPGA area and delay using theoretical derivations," in Quality Electronic Design, 2005. International symposium on, Mar. 2005, pp. 370-374.
6. V. D. J. Davis and J. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI). Part I. Derivation and validation," IEEE Transaction on Electron Devices, vol. 45, no. 3, pp. 580-589, Mar. 1998.
7. D. Stroobandt, A PrioriWire Length Estimates for Digital Design. Kluwer Academic Publishers, 2001.
8. A. E. Gamal, "Two-dimensional stochastic models for interconnections in master-slice integrated circuits," IEEE Transaction on VLSI Systems, vol. 26, no. 4, pp. 127-138, Feb. 1981.
9. S. Balachandran and D. Bhatia, "A priori wirelength estimation and interconnect estimation based on circuit characteristics," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 7, pp. 1054-1065, July 2005.
10. B. Landman and R. Russo, "On a pin virsus block relationship for paritions of logic graphs," IEEE Transaction on Computers, vol. C-20, no. 12, pp. 1469-1479, Dec. 1971.
11. V. Manohararajah, G. Chiu, D. Singh, and S. Brown, "Predicting interconnect delay for physical synthesis in a FPGA cad flow," IEEE Transaction on VLSI Systems, vol. 15, no. 8, pp. 895-903, Aug. 2007.
12. A. Singh and M. Marek-Sadowska, "Efficient circuit clustering for area and power reduction in FPGAs," in Field Programmable Gate Arrays, 2002. ACM/SIGDA International Symposium on, Feb. 2002, pp. 59-66.
13. J. Cong and Y. Ding, "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 1, Jan. 1994.
14. J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. Fang, and J. Rose, "VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling," in Field Programmable Gate Arrays, 2009. ACM/SIGDA International Symposium on, Feb. 2009, pp. 133-142.