An analytical model describing the relationships between logic architecture and FPGA Density

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 221-226

  Lam, Andrew ^a   Wilton, Steven J E ^a   Leong, Philip ^b   Luk, Wayne ^c  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^c IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

TABLE LOOKUP;

ACCURATE; ANALYTICAL MODELS; ARCHITECTURAL PARAMETERS; AREA EFFICIENCIES; CLUSTER SIZES; FPGA ARCHITECTURES; LOGIC ARCHITECTURES; POWERFUL TOOLS; RENT'S RULES; TABLE SIZES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 54949136170     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629935     Document Type: Conference Paper

References (15)

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