Predicting interconnect delay for physical synthesis in a FPGA CAD flow

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 8, 2007, Pages 895-903

  Manohararajah, Valavan ^b   Chiu, Gordon R ^b   Singh, Deshanand P ^b   Brown, Stephen D ^a,b  

^a IEEE

^b Altera Toronto Technology Center   (Canada)

Author keywords

Circuit optimization; Circuit synthesis; Design automation; Field programmable gate arrays (FPGAs); Prediction methods; Programmable logic devices

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RANDOM PROCESSES;

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; DESIGN AUTOMATION; PREDICTION METHODS; PROGRAMMABLE LOGIC DEVICES;

INTERCONNECTION NETWORKS;

EID: 34547452071     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.900744     Document Type: Conference Paper

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