Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 370-374

  Gao, Haixia ^a   Yang, Yintang ^a   Ma, Xiaohua ^a   Dong, Gang ^a  

^a XIDIAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE ANALYSIS; BETTER PERFORMANCE; COMPUTATION MODEL; DELAY MODELS; LUT SIZE; THEORETICAL DERIVATIONS;

EID: 84886682372     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.20     Document Type: Conference Paper

References (16)

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