A study of failure mechanism and reliability assessment for the Panel Level Package (PLP) technology

EuroSime 2007: International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems, 2007

Volumn , Issue , 2007, Pages

  Yew, Ming Chih ^a   Wei, Hsiu Ping ^a   Huang, Ching Shun ^b   Hu, Dyi Chung ^b   Yang, Wen Kung ^b   Chiang, Kou Ning ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b Advanced Chip Engineering Technology Inc   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT TESTING; PLASTICS FILLERS; POLYMERS; SOLDERING ALLOYS; WSI CIRCUITS;

FAILURE MECHANISM; PACKAGING TECHNOLOGY; PANEL LEVEL PACKAGE (PLP) TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 36348960588     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2007.360003     Document Type: Conference Paper

References (15)

1. Badihi, A., "Ultrathin wafer level chip size package", IEEE Tranactions on Advanced Packaging, Vol. 23, No. 2 (2000), pp. 212-214.
2. Lau, J. H. and Lee, R., Chip Scale Package, CSP: Design, Material, Processes, and Applications, McGraw-Hill, (Singapore, 1999).
3. Garrou, P. E., Rogers, W. B., Scheck, D. M., Strandjord, A. J. G., Ida, Y. and Ohba, K., "Stress-Buffer and Passivation Processes for Si and GaAs IC's and Passive Components Using Photosensitive BCB: Process Technology and Reliability Data," IEEE Tranactions on Advanced Packaging, Vol. 22, No. 3 (1999), pp. 487-498.
4. th EuroSimE international conference, Como, Italy, April 2006, pp.328-335.
5. Kawahara, T., "SuperCSP™", IEEE Tranactions on Advanced Packaging, Vol. 23, No. 2 (2000), pp. 215-219.
6. Yew, M. C., Chiu, C. C., Chang, S. M. and Chiang, K. N., "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering and Surface Mount Technology, Vol. 18, No. 3 (2006), pp. 3-13.
7. Yuan, C. A., Han, C. N., Yew, M. C., Chou, C. Y. and Chiang, K. N., "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," IEEE Tranactions on Advanced Packaging, Vol. 28, No. 3 (2005), pp. 387-396.
8. th IEEE IPFA2006 Conference, Singapore, July 2006, pp.223-228.
9. Yew, M. C., Chou, C. Y., Huang, C. S., Yang, W. K. and Chiang, K. N., "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronic Reliability, Vol. 46 (2006), pp. 1874-1879.
10. Lee, W. W., Nguyen, L. T. and Selvaduray, G. S., "Solder joint fatigue models: review and applicability to chip scale packages," Microelectronics Reliability, Vol. 40, No. 2 (2000), pp.231-244.
11. Solomon, H. D., "Fatigue of 60/40 Solder", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-9, No. 4 (1986), pp. 91-104.
12. Fan, X., Pei, M. and Bhatti1, P. K., "Effect of Finite Element Modeling Techniques on Solder Joint Fatigue Life Prediction," Proceedings of 56th Electronic Components and Technology Conference, San Diego, USA, May 2006, pp. 972-980.
13. th EuroSimE international conference, Berlin, Germany, April 2005.
14. Brakke, K.A., "The Surface Evolver", Experimental Mathematics, Vol. 1, No. 2 (1992), pp. 141-165.
15. Chiang, K.N. and Yuan, C.A., "An Overview of Solder Bump Shape Prediction Algorithms with Validations", IEEE Transactions on Advanced Packaging, Vol. 24, No. 2 (2001), pp. 158-162.