Serial sub-threshold circuits for ultra-low-power systems

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 27-32

  Khanna, Sudhanshu ^a   Calhoun, Benton H ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

Bit width; Leakage; Serial systems; Sub threshold; Ultra low power

Indexed keywords

ACTIVE ENERGY; ACTIVE POWER; BIT-WIDTH; LEAKAGE POWER; LOWER ENERGIES; PARALLEL SYSTEM; SHARP CONTRAST; STRONG INVERSION; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; ULTRA LOW POWER;

LOW POWER ELECTRONICS;

POWER ELECTRONICS;

EID: 70449702063     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594241     Document Type: Conference Paper

References (15)

1. A. Wang, B. H. Calhoun, and A. Chandrakasan, Sub-threshold Design for Ultra-Low-Power Systems, Springer, 2006.
2. B.H. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits," JSSC, Vol. 40, No. 9, pp. 1778-1786, September 2005.
3. B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, "Theoretical and practical limits of dynamic voltage scaling," DAC,pp.868-873, 2004.
4. B.H. Calhoun and A. Chandrakasan, "A 256kb Sub-threshold SRAM in 65nm CMOS," ISSCC, pp. 628-629, February 2006.
5. N. Verma and A. Chandrakasan, "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy,"JSSC, Vol. 43, No. 1, pp. 141-149, January 2008.
6. T. H. Kim, J. Liu, J. Keane, and C. H. Kim, "A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing," JSSC, Vol. 43, No. 2, pp. 518-529, Feb 2008.
7. J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM,"JSSC, Vol. 42, No. 10, pp. 2303-2313, October 2007.
8. A. Wang and A. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuit Techiques," ISSCC, pp. 292-293, Feb 2005.
9. Y. Pu, et al., "An Ultra-Low-Energy/Frame Multi-Standard JPEG Co-Processor in 65nm CMOS with Sub/Near-Threshold Power Supply," ISSCC, pp. 146-147, February 2009.
10. M. Seok, et al., "The Phoenix Processor: A 30pW platform for sensor applications," Symp VLSI Circ, pp.188-189, 2008.
11. J.Kwong, et al., "A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter," JSSC, Vol. 44, No. 1, pp. 115-126, January 2009.
12. S. Jocke,et al., "A 2.6-μW Sub-threshold Mixed-signal ECG SoC," Symposium on VLSI Circuits, 2009.
13. R. Amirtharajah, et al., "DSPs for Energy Harvesting Sensors: Applications and Architectures," IEEE Pervasive Computing Magazine, Vol. 4, No. 3, pp. 72-79, 2005.
14. L. Nazhandali, et al, "Energy optimization of subthreshold-voltage sensor network processors," ISCA, pp. 197-207, 2005.
15. W. Zhao and Y. Cao, "New generation of predictive technology modeling for sub-45nm early design exploration," IEEE Trans.on Electron Device, vol. 53, no. 11, pp. 2816-2823, Nov. 2006.