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Volumn , Issue , 2009, Pages 2409-2415

Compact floating-gate learning array with STDP

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DOMAIN; FLOATING GATE TRANSISTORS; FLOATING-GATES; INTEGRATE AND FIRES; OFF-CHIP COMMUNICATION; SPIKE-TIMING-DEPENDENT PLASTICITY; SPIKING NEURAL NETWORKS; SYNAPTIC WEIGHT;

EID: 70449373038     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2009.5178879     Document Type: Conference Paper
Times cited : (15)

References (23)
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  • 4
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  • 10
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    • Hasler, P.1    Dugger, J.2
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    • 0003459788 scopus 로고    scopus 로고
    • Neurally inspired silicon learning: From synapse transistors to learning arrays,
    • Ph. D. dissertation, California Institute of Technology, Pasadena, CA
    • C. Diorio "Neurally inspired silicon learning: From synapse transistors to learning arrays, " Ph. D. dissertation, California Institute of Technology, Pasadena, CA, 1997.
    • (1997)
    • Diorio, C.1
  • 18
    • 33748528992 scopus 로고    scopus 로고
    • Analog Computing Arrays,
    • Ph. D. dissertation, Georgia Institute of Technology, Atlanta, GA
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    • Kucic, M.1
  • 21
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    • Compact silicon neuron circuit with spiking and bursting behaviour
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.