Power-efficient medical image processing using PUMA

2009 IEEE 7th Symposium on Application Specific Processors, SASP 2009

Volumn , Issue , 2009, Pages 29-34

  Dasika, Ganesh ^a   Fan, Kevin ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOMAIN SPECIFIC; GRAPHICS PROCESSING UNITS; MEDICAL IMAGE PROCESSING; MEMORY BANDWIDTHS; MRI RECONSTRUCTION; POPULAR PLATFORM; POWER CONSUMPTION; POWER EFFICIENT;

IMAGE PROCESSING; MEDICAL IMAGING; PROGRAM PROCESSORS;

COMPUTATIONAL EFFICIENCY;

EID: 70350787073     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SASP.2009.5226332     Document Type: Conference Paper

References (25)

1. S. Ciricescu et al. The reconfigurable streaming vector processor (RSVP). In Proc. of the 36th Annual International Symposium on Microarchitecture, pages 141-150, 2003.
2. CNET. The Gizmo Report: NVIDIA's GeForce GTX 280 GPU - introduction, 2008. http://news.cnet.com/8301-13512-3-9969234-23.html.
3. H. Corporaal. TTAs: Missing the ILP complexity wall. Journal of System Architecture, 45(1):949-973, 1999.
4. W. Dally et al. Merrimac: Supercomputing with streams. In Proceedings of the 2003 ACM/IEEE conference on Supercomputing, pages 35-42, 2003.
5. G. Dasika, S. Das, K. Fan, S. Mahlke, and D. Bull. DVFS in loop accelerators using BLADES. In Proc. of the 45th Design Automation Conference, pages 894-897, June 2008.
6. C. Ebeling et al. Mapping applications to the RaPiD configurable architecture. In Proc. of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, pages 106-115, Apr. 1997.
7. K. Fan et al. Cost sensitive modulo scheduling in a loop accelerator synthesis system. In Proc. of the 38th Annual International Symposium on Microarchitecture, pages 219-230, Nov. 2005.
8. K. Fan et al. Modulo scheduling for highly customized datapaths to increase hardware reusability. In Proc. of the 2008 International Symposium on Code Generation and Optimization, pages 124-133, Apr. 2008.
9. J. A. Fisher et al. Custom-fit processors: Letting applications define architectures. In Proc. of the 29th Annual International Symposium on Microarchitecture, pages 324-335, Dec. 1996.
10. S. Goldstein et al. PipeRench: A coprocessor for streaming multimedia acceleration. In Proc. of the 26th Annual International Symposium on Computer Architecture, pages 28-39, June 1999.
11. T. D. Hartley, U. Catalyurek, A. Ruiz, F. Igual, R. Mayo, and M. Ujaldon. Biomedical image analysis on a cooperative cluster of GPUs and multicores. In Proc. of the 2008 International Conference on Supercomputing, pages 15-25, 2008.
12. G. Lu et al. The MorphoSys parallel reconfigurable system. In Proc. of the 5th International Euro-Par Conference, pages 727-734, 1999.
13. A. Mahesri et al. Tradeoffs in designing accelerator architectures for visual computing. In Proc. of the 41st Annual International Symposium on Microarchitecture, pages 164-175, Nov. 2008.
14. B. Mei et al. Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. In Proc. of the 2003 Design, Automation and Test in Europe, pages 296-301, Mar. 2003.
15. Nvidia. CUDA Programming Guide, June 2007. http://developer.download. nvidia.com/compute/cuda.
16. NVIDIA. GeForce GTX 280, 2008. http://www.nvidia.com/object/ productgeforcegtx280us.html.
17. NVIDIA. NVIDIA Tesla S1070, 2008. http://www.nvidia.com/object/ productteslas1070us.html.
18. Nvidia. Cuda Zone, 2009. http://www.nvidia.com/object/cudahome.html.
19. B. R. Rau. Iterative modulo scheduling: An algorithm for software pipelining loops. In Proc. of the 27th Annual International Symposium on Microarchitecture, pages 63-74, Nov. 1994.
20. M. T. Review. Cheap, Portable MRI, 2006. http://www.technologyreview.com/ computing/17499/?a=f.
21. A. Ruiz, M. Ujaldon, L. Cooper, and K. Huang. Non-rigid registration for large sets of microscopic images on graphics processors. Springer Journal of Signal Processing, May 2008.
22. K. Sankaralingam et al. Exploiting ILP, TLP, and DLP using polymorphism in the TRIPS architecture. In Proc. of the 30th Annual International Symposium on Computer Architecture, pages 422-433, June 2003.
23. L. Seiler et al. Larrabee: a many-core x86 architecture for visual computing. ACM Transactions on Graphics, 27(3):1-15, 2008.
24. S. S. Stone et al. Accelerating advanced MRI reconstructions on GPUs. In 2008 Symposium on Computing Frontiers, pages 261-272, 2008.
25. M. Taylor et al. Evaluation of the Raw microprocessor: An exposedwire- delay architecture for ILP and streams. In Proc. of the 31st Annual International Symposium on Computer Architecture, pages 2-13, June 2004.