Performance analysis of buffering schemes in wormhole routers

IEEE Transactions on Computers

Volumn 46, Issue 6, 1997, Pages 687-694

  Boura, Younes M ^a,b   Das, Chita R ^a,c  

^a IEEE   (United States)

^b Siemens Pyramid Information Systems   (United States)

^c The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

Multistage interconnection networks; n dimensional meshes; Router design; Virtual channels; Wormhole switching

Indexed keywords

EID: 33746277518     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.600826     Document Type: Article

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