Statistics in semiconductor test: Going beyond yield

IEEE Design and Test of Computers

Volumn 26, Issue 5, 2009, Pages 64-73

  Daasch, W Robert ^a   Shirley, C Glenn ^a   Nahar, Amit ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Burn in; Computational modeling; Data mining; Data models; Design and test; Mathematical model; Multisite testing; Outlier identification; Outlier screening; Probability density function; Semiconductor device modeling; Statistical modeling; Statistical test; Testing

Indexed keywords

BURN-IN; COMPUTATIONAL MODELING; DATA MODELS; MULTISITE TESTING; OUTLIER IDENTIFICATION; OUTLIER SCREENING; SEMICONDUCTOR DEVICE MODELING; STATISTICAL MODELING;

COMPUTER SIMULATION; MODELS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR SWITCHES; STATISTICAL TESTS; STATISTICS;

PROBABILITY DENSITY FUNCTION;

EID: 70350614084     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.123     Document Type: Article

References (8)

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8. A. Nahar, R. Daasch, and S. Subramaniam, "Burn-in Reduction Using Principal Component Analysis," Proc. IEEE Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 155-164.