Multidimensional test escape rate modeling

IEEE Design and Test of Computers

Volumn 26, Issue 5, 2009, Pages 74-82

  Butler, Kenneth M ^a   Carulli Jr , John M ^a   Saxena, Jayashree ^a   Nahar, Amit ^a   Daasch, W Robert ^b  

^a TEXAS INSTRUMENTS   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

Automatic test pattern generation; Circuit faults; Computational modeling; Data models; Defect level; Defective parts per million (DPPM); Design and test; Fault coverage; Integrated circuit modeling; Production; Test escapes; Yield

Indexed keywords

CIRCUIT FAULTS; COMPUTATIONAL MODELING; DATA MODELS; DEFECT LEVEL; DEFECTIVE PARTS PER MILLION (DPPM); FAULT COVERAGE; INTEGRATED CIRCUIT MODELING; TEST ESCAPES; YIELD;

DATA COMPRESSION; INTEGRATED CIRCUITS; MODELS; PULSE POSITION MODULATION; TESTING;

AUTOMATIC TEST PATTERN GENERATION;

EID: 70350593697     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2009.118     Document Type: Article

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