SCOPUS 정보 검색 플랫폼

IEEE Design and Test of Computers

Volumn 19, Issue 5, 2002, Pages 74-81

Neighborhood selection for IDDQ outlier screening at wafer sort

(4) Daasch, W Robert b McNames, James c Madge, Robert a Cota, Kevin a

a LSI Logic Corp

b Department of Electrical and Computer Engineering (United States)

c NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; ELECTRIC CURRENT MEASUREMENT; ESTIMATION; FAILURE ANALYSIS; GRAPH THEORY; LEAKAGE CURRENTS; MATHEMATICAL MODELS; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS; VECTORS;

NEAREST NEIGHBOR RESIDUAL METHOD; STATISTICAL POST-PROCESSING METHOD; TRANSISTOR DENSITY; WAFER PATTERNS;

INTEGRATED CIRCUIT TESTING;

EID: 0036734210 PISSN: 07407475 EISSN: None Source Type: Journal
DOI: 10.1109/MDT.2002.1033795 Document Type: Article

Times cited : (18)

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2
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4
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5
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6
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7
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11
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12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.