Analytical model for multi-site efficiency with parallel to serial test times, yield and clustering

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 270-275

  Velamati, Naveen ^a   Daasch, Robert ^a  

^a PORTLAND STATE UNIVERSITY   (United States)

Author keywords

Average test time; Multi site testing; Test cost reduction; Test time reduction; Yield ramp

Indexed keywords

AVERAGE TEST TIME; MULTI-SITE TESTING; TEST COST REDUCTION; TEST TIME REDUCTION; YIELD RAMP;

COST REDUCTION;

TESTING;

EID: 70350417359     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.42     Document Type: Conference Paper

References (8)

1. Semiconductor Industry Association (SIA), Test & Test Equipment. International Technology Roadmap for Semiconductors, 2005.
2. G. Moore, "No exponential is forever: But "forever" can be delayed," in IEEE Solid-State Circuits Conference, vol. 1, 2003, pp. 20-23.
3. M. Nourani and J. Chin, "Testing high speed socs using low-speedates," In Proceedings, IEEE VLSI Test Symposium, p. 133138, 2002.
4. F. J. M. Hamidreza Hashempour and F. Lombardi, "Analysis and evaluation of multisite testing for vlsi," IEEE Transactions On Instrumentation And Measurement, pp. 1770-1778, 2005.
5. J. R. E.H. Volkerink, A. Khoche and K. Hilliges, "Test economics for multi-site test with modern cost reduction techniques," IEEE VLSI Test Symposium, pp. 411-416, 2002.
6. C. H. Stapper, "Modeling of integrated circuit defect sensitivities," IBM Journal of Research and Development, vol. 27, pp. 549-557, 1983.
7. G. Amdahl. (1967) Amdahl's law. [Online]. Available: http://en.wikipedia. org/wiki/Amdahls-law
8. J. Hammersley and D. Handscomb, Monte Carlo Methods. Boston: Methuen, 1964.