Towards a C++-based design methodology facilitating sequential equivalence checking

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 93-96

  Georgelin, Philippe ^a   Krishnaswamy, Venkat ^b  

^a STMICROELECTRONICS   (France)

^b Calypto Design Systems   (United States)

Author keywords

Modeling methodology; Sequential equivalence checking

Indexed keywords

ABSTRACTING; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; SOFTWARE PROTOTYPING; VERIFICATION;

MODELING METHODOLOGY; RTL VERIFICATION; SEQUENTIAL EQUIVALENCE CHECKING; SYSTEMS-ON-CHIP;

C (PROGRAMMING LANGUAGE);

EID: 34547150781     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146938     Document Type: Conference Paper

References (2)

1. David Maliniak, "Equivalence Checker Handles Sequential Logic", Electronic Design, May 12, 2005
2. Frank Ghenassia (ed), "Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems", Springer 1st Edition, 2005