Maximizing full-chip simulation signal visibility for efficient debug

2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers

Volumn , Issue , 2007, Pages

  Hsu, Yu Chin ^a  

^a Novas Software Inc

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SIMULATION; DATA ACQUISITION; ERROR ANALYSIS; PROGRAM DEBUGGING; SIGNAL ANALYSIS;

BLOCK LEVEL SIMULATION; SIMULATION SIGNAL VISIBILITY; SYSTEM ON CHIP (SOC);

INTEGRATED CIRCUITS;

EID: 34648813273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2007.373207     Document Type: Conference Paper

References (0)