A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs

IEICE Electronics Express

Volumn 6, Issue 19, 2009, Pages 1414-1420

  Jo, Kwan Hee ^a   Bong, Ji Hye ^a   Min, Kyeong Sik ^a   Kang, Sung Mo ^b  

^a Kookmin University   (South Korea)

^b University of California   (United States)

Author keywords

Macromodel; Multi Level Cell; Phase change RAMs; Resistive memories; Verilog A model

Indexed keywords

MACROMODEL; MULTI LEVEL CELL; PHASE CHANGE RAMS; RESISTIVE MEMORIES; VERILOG-A MODEL;

CELL MEMBRANES; COMPUTER SIMULATION; COMPUTERS; RANDOM ACCESS STORAGE;

SPICE;

EID: 70350244378     PISSN: None     EISSN: 13492543     Source Type: Journal    
DOI: 10.1587/elex.6.1414     Document Type: Article

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