Compact HSPICE macromodel of resistive RAM

IEICE Electronics Express

Volumn 4, Issue 19, 2007, Pages 600-605

  Lee, Jin Gu ^a   Kim, Dae Hwan ^a   Lee, Jae Gab ^a   Kim, Dong Myong ^a   Min, Kyeong Sik ^a  

^a Kookmin University   (South Korea)

Author keywords

HSPICE macromodel; Phase change RAM; Resistive RAM; Resistive switching

Indexed keywords

EID: 36249004281     PISSN: None     EISSN: 13492543     Source Type: Journal    
DOI: 10.1587/elex.4.600     Document Type: Article

References (5)

1. I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S. O. Park, H. S. Kim, I. K. Yoo, U.-In. Chung, and J. T. Moon, "Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses," IEEE Int. IEDM Tech. Digest, pp. 587-590, Dec. 2004.
2. X. Q. Wei, L. P. Shi, R. Walia, T. C. Chorig, R. Zhao, X. S. Miao, and B. S. Quek, "HSPICE macromodel of PCRAM for binary and multilevel storage," IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 56-62, Jan. 2006.
3. HSPICE simulation and analysis user guide, March 2006.
4. R. A. Cobley and C. D. Wright, "Parameterized SPICE model for a phase-change RAM device," IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 112-118, Jan. 2006.
5. 2 thin films," Appl. Phys. Lett., vol. 89, 012906, 2006.