A 0.1-5GHz dual-VCO software-defined ΣΔ frequency synthesizer in 45nm digital CMOS

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2009, Pages 321-324

  Nuzzo, Pierluigi ^a   Vengattaramane, Kameswaran ^a,b   Ingels, Mark ^a   Giannini, Vito ^a   Steyaert, Michiel ^b   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Phase locked loops; Programmable dividers; Software defined radio; Voltage controlled oscillators

Indexed keywords

AREA COST; CURRENT CONSUMPTION; DIGITAL CMOS; DIGITAL TECHNOLOGIES; HIGH FLEXIBILITY; PROGRAMMABLE DIVIDER; PROGRAMMABLE DIVIDERS; SCALABLE IMPLEMENTATION; SOFTWARE-DEFINED RADIO; SOFTWARE-DEFINED RADIOS; SYNTHESIZER ARCHITECTURE; TUNING RANGES; VOLTAGE CONTROLLED OSCILLATORS; WIDE BAND FREQUENCIES; WIRELESS STANDARDS;

COMPUTER SOFTWARE; DESIGN; DIGITAL INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; PHASE SHIFT; RADIO; RADIO RECEIVERS; RADIO WAVES; SOFTWARE ARCHITECTURE; VARIABLE FREQUENCY OSCILLATORS;

VOLTAGE DIVIDERS;

EID: 70350228522     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2009.5135549     Document Type: Conference Paper

References (12)

1. 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS," ISSCC Dig. of Technical Papers, pp. 208-209, Feb. 2008.
2. S. Kousai et al., "A 1.2V 0.2-to-6.3GHz transceiver with less than -29.5dB EVM@-3dBm and a choke/coil-Less Pre-Power Amplifier," ISSCC Dig. of Tech. Papers, pp. 214-215, Feb. 2008.
3. 2 0.1-5GHz SDR Receiver in 45nm Digital CMOS," ISSCC Dig. of Technical Papers, Feb. 2009.
4. J. Craninckx, M. Liu, D. Hauspie, et al., "A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μ m CMOS," ISSCC Dig. of Technical Papers, pp. 346-347, Feb. 2007.
5. M. Ingels et al., "A CMOS 100 MHz to 6 GHz Software Defined Radio analog front-end with integrated Pre-Power Amplifier", Proc. of Europ. Solid-State Cir. Conf., pp. 436-439, Sept. 2007.
6. R. B. Staszewski, et al., "Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process," IEEE Trans. on Cir. and Syst. - II, vol. 50, no. 11, Nov. 2003.
7. D. Hauspie, E.-C. Park and J. Craninckx, "Wideband VCO with Simultaneous Switching of Frequency Band, Active Core and Varactor Size," IEEE Journal of Solid-State Circuits, July 2007.
8. J. Van Driessche, J. Craninckx and B. Come, "Analysis and Key Specifications of a Novel Frequency Synthesizer Architecture for Multi-Standard Transceivers," IEEE Radio and Wireless Symposium, pp. 481-484, January 2006.
9. A. Mazzanti, P. Andreani, "Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise," IEEE Journal of Solid-State Circuits, vol.43, no.12, pp. 2716-2729, Dec. 2008.
10. J. Craninckx and M. Steyeart, Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, Dordrecht, the Netherlands, 1998.
11. C. S. Vaucher, et. al., "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology", IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000.
12. Y.-C. Yang, et. al., "A Quantization Noise Suppression Technique for Fractional-N Frequency Synthesizers", IEEE Journal of Solid State Circuits, Vol. 41, No. 11, pp.2500-2510, Nov. 2006.