Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 3162-3165

  Lin, Tong ^a   Chong, Kwen Siong ^a   Gwee, Bah Hwee ^a   Chang, Joseph S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL BLOCKS; CONTROL OVERHEAD; CONTROLLED GATING; DATA INPUT; DELAY OVERHEADS; FINE-GRAINED POWER; INPUT RATE; LEAKAGE POWER; NMOS TRANSISTORS; PMOS TRANSISTORS; POWER GATINGS; POWER REDUCTIONS; SHORT-CIRCUIT POWER;

COMPUTER SIMULATION; PIPELINES; TRANSISTORS;

LOGIC CIRCUITS;

EID: 70350192273     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5118474     Document Type: Conference Paper

References (12)

1. K.-S. Chong, B.-H. Gwee, and J. S. Chang, "A micropower lowvoltage multiplier with reduced spurious switching," IEEE Trans.VLSI Syst., v13, n2, pp. 256--265, Feb. 2005.
2. V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. Int. Symp. Low Power Electronics and Design, 1999, pp. 163-168.
3. H. S. Deogun, D. Sylvester, and K. Nowka, "Fine grained multithreshold CMOS for enhanced leakage reduction," IEEE ISCAS, 2006, pp. 4.
4. Y. Oowaki et al., "A sub-0.1um Circuit Design with Substrate-Over-Biasing," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., 1998, pp. 88-89.
5. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in Proc. Int. Symp. Low Power Electronics and Design, 1998, pp. 239-244.
6. M. Borah, R. M. Owens, and M. J. Irwin, "Transistor sizing for low power CMOS circuits,", IEEE Tran. CAD of Integrated Circuits and Systems, vol. 15, pp. 665-671, 1996.
7. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
8. T. Enomoto, Y. Oka, and H. Shikano, "A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications," IEEE J. Solid-State Circuits, vol. 38, pp. 1220-1226, 2003.
9. T.Kuroda et al., "A 0.9V 150MHz 10mW 4mm 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., pp. 166-167, 1996.
10. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, pp. 305-327, 2003.
11. A. J. Martin and M. Nystrom, "Asynchronous Techniques for System-on-Chip Design," Proc. IEEE, vol. 94, pp. 1089-1120, 2006.
12. K.-S. Chong, B.-H. Gwee, and J. S. Chang, "Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors," IEEE J. Solid-State Circuits, vol. 42, pp. 2034-2045, 2007.